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| White Electronic Designs WV3EG64M64ETSU-D4 PRELIMINARY* 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM FEATURES Fast data transfer rate: PC3200 & PC2700 Clock speeds of 200MHz & 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency : DDR400 (3 clock), DDR333 (2.5 clock) Programmable Burst Length (2, 4 or 8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh, 7.8s refresh interval (8K (64ms refresh) Serial presence detect (SPD) with EEPROM Serial presence detect with EEPROM VCC = VCCQ = +2.5V 0.2V (166MHz) VCC = VCCQ = +2.6V 0.1V (200MHz) Gold edge contacts JEDEC standard 200 pin, small-outline, SO-DIMM package * PCB height option: D4: 31.75 mm (1.25") TYP * This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION The WV3EG64M64ETSU is a 64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eight 64Mx8 DDR SDRAMs TSOP-II packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option OPERATING FREQUENCIES DDR400@CL=3 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 DDR333@CL2.5 166MHz 2.5-3-3 March 2006 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 51 VSS 101 A9 151 DQ42 1 VREF 2 VREF 52 VSS 102 A8 152 DQ46 53 DQ19 103 VSS 153 DQ43 3 VSS 4 VSS 54 DQ23 104 VSS 154 DQ47 5 DQ0 55 DQ24 105 A7 155 VCC 6 DQ4 56 DQ28 106 A6 156 VCC 7 DQ1 57 VCC 107 A5 157 VCC 8 DQ5 58 VCC 108 A4 158 CK1# 9 VCC 59 DQ25 109 A3 159 VSS 10 VCC 60 DQ29 110 A2 160 CK1 11 DQS0 61 DQS3 111 A1 161 VSS 12 DM0 62 DM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VCC 163 DQ48 14 DQ6 64 VSS 114 VCC 164 DQ52 65 DQ26 115 A10 165 DQ49 15 VSS 16 VSS 66 DQ30 116 BA1 166 DQ53 17 DQ3 67 DQ27 117 BA0 167 VCC 18 DQ7 68 DQ31 118 RAS# 168 VCC 19 DQ8 69 VCC 119 WE# 169 DQS6 20 DQ12 70 VCC 120 CAS# 170 DM6 21 VCC 71 NC 121 CS0# 171 DQ50 22 VCC 72 NC 122 NC 172 DQ54 23 DQ9 73 NC 123 NC 173 VSS 24 DQ13 74 NC 124 NC 174 VSS 25 DQS1 75 VSS 125 VSS 175 DQ51 26 DM1 76 VSS 126 VSS 176 DQ55 27 VSS 77 NC 127 DQ32 177 DQ56 78 NC 128 DQ36 178 DQ60 28 VSS 29 DQ10 79 NC 129 DQ33 179 VCC 30 DQ14 80 NC 130 DQ37 180 VCC 31 DQ11 81 VCC 131 VCC 181 DQ57 32 DQ15 82 VCC 132 VCC 182 DQ61 83 NC 133 DQS4 183 DQS7 33 VCC 34 VCC 84 NC 134 DM4 184 DM7 35 CK0 85 NC 135 DQ34 185 VSS 36 VCC 86 NC 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 39 VSS 89 NC 139 DQ35 189 DQ59 40 VSS 90 VSS 140 DQ39 190 DQ63 41 DQ16 91 NC 141 DQ40 191 VCC 42 DQ20 92 VCC 142 DQ44 192 VCC 43 DQ17 93 VCC 143 VCC 193 SDA 44 DQ21 94 VCC 144 VCC 194 SA0 45 VCC 95 NC 145 DQ41 195 SCL 46 VCC 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VCCSPD 48 DM2 98 NC 148 DM5 198 SA2 49 DQ18 99 A12 149 VSS 199 NC 50 DQ22 100 A11 150 VSS 200 NC WV3EG64M64ETSU-D4 PRELIMINARY PIN NAMES Symbol A0-A12 BA0, BA1 DQ0-DQ63 CK0, CK0# CK1, CK1# CKE0 CS0# WE#, CAS#, RAS# DQS0-DQS7 DM0-DM7 VCC VCCQ VCCSPD VREF VSS SCL SA0-SA2 SDA NC Description Address input Bank Address Input/Output: Data I/Os, Data bus Clock Input Clock Enable Input Chip Select Input Command Input Data Strobe Data Write Mask Supply: Power Supply Power Supply for DQS Supply: Serial EEPROM Positive Power Supply Supply: SSTL_2 reference voltage Supply: Ground Serial Clock Presence Detect Address Input Input/Output: Serial PresenceDetect Data No Connect March 2006 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM WV3EG64M64ETSU-D4 PRELIMINARY CS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS4 DM4 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS5 DM5 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS6 DM6 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQS7 DM7 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# CKE0 BA0 - BA1 A0 - A12 RAS# CAS# WE# CKE0: DDR SDRAMs BA0 - BA1: DDR SDRAMs A0 - A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs WE#: DDR SDRAMs Serial PD SCL SP A0 SA0 A1 SA1 A2 SA2 SDA 120 Ohms VCCSPD VCC/VCCQ VREF VSS SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs CK0 CK0# 120 Ohms DDR SDRAM x 4 CK1 CK1# DDR SDRAM x 4 Note: 1. All resistor values are 22 unless otherwise specified. March 2006 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DC OPERATING CONDITIONS TA = 0C to 70C Parameter/Condition Supply Voltage DDR400 (nominal VCC 2.6) I/O Supply Voltage DDR400 (nominal VCC 2.6) Supply Voltage DDR333 I/O Supply Voltage DDR333 I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input voltage level, CK and CK# Input differential voltage, CK and CK# Input crossing point voltage, CK and CK# Addr, CAS#, RAS#, WE# CS#, CKE CK, CK# DM Symbol VCC VCCQ VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) WV3EG64M64ETSU-D4 PRELIMINARY Min 2.5 2.5 2.3 2.3 0.49 x VCCQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 -0.3 -0.3 -16 Max 2.7 2.7 2.7 2.7 0.51 x VCCQ VREF + 0.04 VCC + 0.30 VREF - 0.15 VCCQ + 0.30 VCCQ + 0.60 VCCQ + 0.60 16 16 8 2 5 -- -- -- -- Units V V V V V V V V V V V A A A A A mA mA mA mA Notes 1 2 3 Input leakage current II Output leakage current Output high current (normal strength) VOUT = v + 0.84V Output high current (normal strength) VOUT = v - 0.84V Output high current (half strength) VOUT = VTT + 0.45V Output high current (half strength) VOUT = VTT - 0.45V IOZ IOH IOL VOH VOL -16 -8 -2 -5 -16.8 -16.8 -9 9 Notes: 1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed +/-2% of the DC values. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level of CK#. 4. Industrial grade modules are specified to a DRAM tCASE of 85C and -40C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any in relative to VSS Voltage on VCC & VCCQ supply relative to VSS Voltage on VREF supply relative to VSS Storage temperature Operating temperature Power dissipation Short circuit output current Symbol VIN, VOUT VCC, VCCQ VREF TSTG TA PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 0 ~ 70 8 50 Units V V V C C W mA Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed. Functional operation should be restricted to recommended operating condition. Exposing to higher than recommended voltage for extended periods of time could affect device reliability. March 2006 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs INPUT/OUTPUT CAPACITANCE TA = 25C, f = 100MHz Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, RAS#, CAS# WE#) Input capacitance (CKE0) Input capacitance (CS0#) Input capacitance (CK0, CK0#, CK1, CK1#) Input capacitance (DM0 ~ DM7) Input capacitance (DQ0 ~ DQ63), (DQS0 ~ DQS7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 WV3EG64M64ETSU-D4 PRELIMINARY Min 20 20 20 12 8 8 Max 28 28 28 16 9 9 Units pF pF pF pF pF pF Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed. Functional operation should be restricted to recommended operating condition. Exposing to higher than recommended voltage for extended periods of time could affect device reliability. AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Differential Voltage, CK and CK# inputs Input crossing point voltage, CK and CK# input Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF + 0.31 0.7 0.5*VCCQ - 0.2 Max VREF - 0.31 VCCQ + 0.6 0.5*VCCQ + 0.2 Units V V V V March 2006 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M64ETSU-D4 PRELIMINARY ICC SPECIFICATIONS AND CONDITIONS 0C TA +70C DDR400: VCC = VCCQ = +2.6V 0.1V Max Symbol Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH BURST CURRENT: SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands tREFC = tRFC (MIN) DDR400 @CL=3 960 1,200 40 240 360 480 1,240 1,400 1,760 40 3,080 Max DDR333 @CL=2.5 840 1,080 40 240 200 360 1,120 1,200 1,640 40 2,880 Units ICC0 ICC1 ICC2P ICC2F ICC3P ICC3N ICC4R ICC4W ICC5 ICC6 ICC7 mA mA mA mA mA mA mA mA mA mA mA Notes: ICC parameters are based on SAMSUNG components. Other DRAM manufactures parameter may be different March 2006 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M64ETSU-D4 PRELIMINARY ICC SPECIFICATIONS AND CONDITIONS 0C TA +70C, DDR400: VCC = VCCQ = +2.6V 0.1V Max Symbol Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH BURST CURRENT: SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands tREFC = tRFC (MIN) DDR400 @CL=3 TBD Max DDR333 @CL=2.5 1,040 1,280 40 360 280 400 1,320 1,400 2,320 40 3,240 Units ICC0 ICC1 ICC2P ICC2F ICC3P ICC3N ICC4R ICC4W ICC5 ICC6 ICC7 mA mA mA mA mA mA mA mA mA mA mA TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Notes: ICC parameters are based on MICRON components. Other DRAM manufactures parameter may be different March 2006 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M64ETSU-D4 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 0C TA +70C; AC Characteristics Parameter Row Cycle Time Refresh row cycle time Row active RAS# to CAS# delay Row percharge time Row active to row active delay Write recovery time Last data in to READ command Clock cycle time CL = 2.5 CL = 3 Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH Min 55 70 40 15 15 10 15 2 6 5 0.45 0.45 -0.55 -0.65 0.9 0.4 0.72 0 0.25 0.2 0.2 403 Max Min 60 72 42 18 18 12 15 1 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 335 Max Units tCK ps ps tCK ns ns ns ns ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK 70K 70K CK high-level width CK low-level width Access window of DQS from CK/CK# Access window of DQs from CK/CK# DQS-DQ skew, DQS to last DQ valid, per group, per access Read preamble Read postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge to CK rising-hold time 12 10 0.55 0.55 +0.55 +0.65 0.4 1.1 0.6 1.28 12 0.55 0.55 +0.6 +0.7 0.4 1.1 0.6 1.25 Notes: Industrial grade modules are specified to a DRAM tCASE of 85C and -40C Continued on next page March 2006 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M64ETSU-D4 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 0C TA +70C AC Characteristics Parameter DQS-in high level width DQS-in low level width Address and control input setup time (fast) Address and control input hold time (fast) Address and control input setup time (slow) Address and control input hold time (slow) Data-out high-impedance time from CK/CK# Data-out low-impedance time from CK/CK# Mode register set cycle DQ and DM input setup time to DQS DQ and DM input hold time to DQS Control & address input pulse width DQ & DM input pulse width Exit self refresh to non-Read command Exit self refresh to Read command Refresh interval time Output DQS valid window Clock Half period Data hold skew factor DQS write postable Active read with auto precharge command Auto precharge write recovery + precharge time Symbol tDQSH tDQSL tISF tIHF tISs tIHS tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL Min 0.35 0.35 0.6 0.6 0.7 0.7 -0.65 10 0.4 0.4 2.2 1.75 75 200 7.8 tHP - tQHS tCL(MIN) or tCH(MAX) 0.4 15 tWR/tCK + 403 Max Min 0.35 0.35 0.75 0.75 0.8 0.8 -0.70 12 0.45 0.45 2.2 1.75 75 200 335 Max Units tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK s ns ns ns ns ns tCK +0.65 +0.70 7.8 tHP - tQHS tCL(MIN) or tCH(MAX) 0.5 0.6 0.4 18 tWR/tCK + 0.5 0.6 tRP/tCK Notes: Industrial grade modules are specified to a DRAM tCASE of 85C and -40C tRP/tCK March 2006 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M64ETSU-D4 PRELIMINARY ORDERING INFORMATION FOR D4 Part Number WV3EG64M64ETSU403D4xxG WV3EG64M64ETSU335D4xxG Speed 200MHz/400Mbps 166MHz/333Mbps CAS Latency 3 2.5 tRCD 3 3 tRP 3 3 Height* 31.75 (1.25") TYP 31.75 (1.25") TYP NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "-x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option 200-PIN DDR2 SO-DIMM DIMENSIONS FRONT VIEW 67.75 (2.667) 67.45 (2.656) 3.80 (0.150) MAX 4.10 (0.161) 2X) ( 3.90( 0.154) 1.80 (0.071) (2X) 31.90 (1.256) 31.60 (1.244) 20.00 (0.787) TYP 6.000 (.236) 2.55 (0.100) 2.15 (0.085) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP PIN 1 0.45 (0.018) 0.60 (0.024) TYP TYP 2.504 (63.60) TYP PIN 199 BACK VIEW PIN 200 0.165 (4.2) TYP 1.866 (47.40) TYP 0.449 (11.40) TYP PIN 2 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) March 2006 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PART NUMBERING GUIDE WV3EG64M64ETSU-D4 PRELIMINARY W 3 E G 64M 64 E T S U xxx D4 x x G WEDC MEMORY (SDRAM) DDR GOLD DEPTH) BUS WIDTH x8 TSOP (400M/bs = VCC/VCCQ = +2.6V 0.1V) 2.5V UNBUFFERED SPEED (Mbs) PACKAGE 200 PIN TEMPERATURE RANGE (Blank = 0C - 70C ambient) (I = -40C to 85C DRAM case temp) COMPONENT VENDOR NAME (M = MICRON) (S = SAMSUNG) G = RoHS COMPLIANT March 2006 Rev. 0 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 512MB - 64Mx64 DDR SDRAM, UNBUFFERED SO-DIMM WV3EG64M64ETSU-D4 PRELIMINARY Revision History Rev # Rev 0 History Created Release Date 3-06 Status Preliminary March 2006 Rev. 0 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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